QPU Lens

Dispatch → QPUs

Workgroups Color by

Simplified model: workgroups go round-robin to slices; each workgroup is split into 16-invocation subgroups that run as one QPU thread (4 lanes × 4 cycles).

Uniforms

edits rewrite the // @uniform lines

Replay

Pin baseline

Analysis

what the QPUs would actually do

Memory access sites

Branches & loops

Threads / QPU

Memory hierarchy

data flows DRAM → L2 → TMU → QPU registers (latencies are illustrative)

Clock timeline

QPUs

Memory → VPM → QPU

DMA moves rows between memory and the VPM; QPUs read and write the VPM one 16-lane vector at a time

Clock timeline

each column is one clock · each instruction = 4 clocks · click to jump